Design and Implementation of AHD–2494, a 24–bit RISC Processor on a VLSI Chip

This paper presents the work done by the three students: Ahmed El-Wakeel, Hossam Fahmy and Dalia El-dib during their graduation project. A 24 bit RISC processor following the Von Neumann architecture and having two modes of operation (operating system mode/user mode) was designed. It has 16 general purpose registers and executes one instruction per clock cycle. The instruction set contains 16 instructions all of fixed 24 bit length. It follows a load/store architecture. Simulation results show that a clock speed of 10 MHz driving a 50pf load off-chip capacitance can be used. The implementation was done on a semicustom process, the sea-of-gates fishbone image which is a 1.6 micron CMOS technology with two metal layers. The layout and layer interconnects were done manually in the basic cells. The full design consists of about 120 000 transistors.